/*
 * Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2022-08-14     RiceChen     first version
 */

#ifndef __BOARD_H__
#define __BOARD_H__

#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include <hal_common.h>

#ifdef __cplusplus
extern "C" {
#endif

#define MM32_FLASH_START_ADRESS       ((uint32_t)0x08000000)
#define MM32_FLASH_SIZE               (256 * 1024)
#define MM32_FLASH_END_ADDRESS        ((uint32_t)(MM32_FLASH_START_ADRESS + MM32_FLASH_SIZE))

#define MM32_SRAM1_SIZE               (112)
#define MM32_SRAM1_START              (0x30000000)
#define MM32_SRAM1_END                (MM32_SRAM1_START + MM32_SRAM1_SIZE * 1024)

#if defined(__ARMCC_VERSION)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN      (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN      ((void *)&__bss_end)
#endif

#define HEAP_END                       MM32_SRAM1_END

#define CLOCK_SYS_FREQ         120000000u
#define CLOCK_SYSTICK_FREQ     (CLOCK_SYS_FREQ/8u)
#define CLOCK_AHB1_FREQ        120000000u
#define CLOCK_AHB2_FREQ        120000000u
#define CLOCK_AHB3_FREQ        120000000u
#define CLOCK_APB1_FREQ        60000000u
#define CLOCK_APB2_FREQ        60000000u

void SystemClock_Config(void);

#ifdef __cplusplus
}
#endif

#endif

